Method and apparatus for low temperature copper to copper bonding

ABSTRACT

A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part application of co-pendingnon-provisional application Ser. No. 10/610,743 filed Jul. 2, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of 3-dimensional stackedsubstrates and semiconductor packaging.

2. Discussion of Related Art

Three-dimensional stacked substrate (3D-SS) arrangements are electronicdevices having a plurality of stacked semiconductor die/chips/wafersthat are physically and electrically interconnected with one another.The drive toward achieving 3D-SSs is in its infancy, and numeroustechnical problems for achieving 3D-SSs have not yet been satisfactorilyresolved.

Techniques similar to those used for a 3D-SS may also be used inphysically and electrically connecting a die or 3D stack of die to apackage substrate.

With each generation, as devices operate at lower voltages and higherfrequencies, current levels at the die-die and/or at the die-packageinterface are increasing. This may cause EM (electromigration) failurefor a 3D-SS at the die-die interface, or may cause EM failure at thedie-package interface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of a three-dimensional cross-sectional view ofa 3D-IC interconnect structure.

FIGS. 2-4 are cross-sections illustrative of a disadvantageous situationthat may negatively affect manufacturability and/or reliability of3D-ICs.

FIGS. 5-6 are cross-sections illustrative of an embodiment which mayenhance manufacturability and/or reliability of 3D-ICs.

FIGS. 7-8 are cross-sections illustrative of an embodiment which mayenhance manufacturability and/or reliability of 3D-ICs.

FIG. 9 is an illustration of a three-dimensional cross-sectional view ofa die-package interconnect structure.

FIGS. 10-12 are cross-sections illustrative of embodiments which mayenhance manufacturability and/or reliability of die-package interconnectstructures.

FIG. 13 is an illustration of a system which may include embodiments ofthe present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following description, numerous specific details are set forth,such as exact process steps, in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that these specific details need not be employedto practice the present invention. In other instances, well knowncomponents or methods have not been described in detail in order toavoid unnecessarily obscuring the present invention. When appropriate,like reference numerals and characters may be used to designateidentical, corresponding or similar components in differing figuredrawings. Further, in the detailed description to follow, examplesizes/values/ranges/materials may be given, although the presentinvention is not limited to the same. As manufacturing techniques (e.g.,photolithography) mature over time, it is expected that devices,apparatus, etc., of smaller size than those discussed could bemanufactured.

Copper to copper bonding is considered to be one of the potentialcandidates in the fabrication of 3D SSs. Copper to copper bonding isalso a candidate for fabrication of die to package interconnectstructures. However, copper has a tendency to develop oxide and othercontaminants during manufacturing processes. Copper also has a tendencyto diffuse very fast through both silicon and interlayer dielectricsthereby leading to serious reliability concerns due to induced shortcircuits or high leakage currents. Electromigration is also a problemfor copper structures without passivation. This disclosure sets forth amethod and apparatus which may minimize the problems related toreliability concerns arising from excessive copper diffusion,electromigration and/or corrosion problems related to bonded structures,from a substrate (e.g., die, wafer, package) bonding perspective.

In practice, many different types of substrate stacks may bemanufactured using copper interconnects. For example, if the stackedsubstrates are die, then it can be said that a three-dimensional die(3D-D), is formed. An alternative term may be a three-dimensionalintegrated circuit (3D IC). Individual semiconductor wafers may also bestacked/bonded to form a three-dimensional wafer stack (3D WS), or diecould be bonded to wafers. Additionally, individual die or 3D-ICs may bebonded to a package substrate.

FIG. 1 illustrates an example three-dimensional cross-sectional view 100of a small portion of a 3D-IC bonded using copper interconnectstructures according to an embodiment of the present invention. Only avery small portion of the 3D-IC is shown for the sake of simplicity andbrevity. A first IC substrate 102 and a second IC substrate 104 arebonded together to form a 3D-IC. The inter-substrate spacing 112 may bein the range of 0.01-0.20 μm. Although not illustrated, the substrates102, 104 may have predetermined integrated circuits, such as transistorsor capacitors, formed thereon. While a 3D stack of only two ICsubstrates is shown for simplicity, the present invention is by no meanslimited to a two-substrate stack; a greater number ofstacked/interconnected IC substrates may be accomplished withembodiments of the present invention, including stacks of three or moreIC substrates.

The first IC substrate 102 has a plurality of interconnection pillars106, and the second IC substrate 104 has a plurality of opposinginterconnection pillars 108. The opposing interconnection pillars arejoined at bonds or interfaces 110. The inter-pillar spacing 114 mayrange from 1 to 50 μm, or more particularly may be between 3-5 μm. Theinterconnection pillars may be formed, for example, by first formingcopper plugs within etched vias in a surface of each IC substrate, thenchemically-mechanically polishing (CMP) the plugs/surface in an attemptto achieve plug surfaces in a common plane (planarization), and thenperforming a selective removal (e.g. selective etching) process toresult in slight surface elimination of only substrate material toachieve raised copper pillars.

The first and second IC substrates 102, 104 may then be preciselyaligned, aligning opposing pillars, and bonded together, typically atelevated temperatures and/or under pressure, to form individualelectrical and mechanical interconnections between each interconnectionpillar pair 106, 108. While only a few interconnection pillar pairs 106,108 are shown for simplicity, the actual practice of 3D-IC bonding mayinvolve as few as tens or as much as ten of millions of interconnectionpillar pairs.

The interconnection pillars 106, 108 may both be copper (Cu) pillarinterconnections. The pillars may be other materials as well, such asaluminum (Al), gold (Au), silver (Ag), or alloys of two or moreelements. While embodiments of the interconnection pillars 106, 108 aredescribed as being made of a mutually common material such as copper,practice of embodiments of the present invention is not limited thereto.The interconnection pillars 106, 108 may be made of mutually differingmaterials, for example, one pillar may be gold while the other iscopper, so long as the two materials may physically bond together toform an electrical conduction path.

The bonded interconnection pillars provide a rigid and permanentphysical bonding of the opposing IC substrates 102, 104 together, whileindividual bonded interconnection pillars may each provide an electricalconduction path to electrically interconnect portions of circuits on theopposing substrates 102, 104.

For 3D-ICs to gain widespread acceptance in the industry, they mustoffer both a reasonable level of manufacturability and a high level ofreliability. FIGS. 2 and 3 are illustrative of a disadvantageoussituation that may negatively affect manufacturability and/orreliability. Contaminants may negatively interfere with, and thus affectthe integrity of, physical bonding of the opposing substrates 102, 104together, and/or may negatively affect an integrity or quality ofelectrical conduction paths of the individual bonded interconnectionpillars.

FIG. 2 is a cross-sectional view of opposing substrates 102 and 104prior to bonding, illustrating undesirable contaminants 120 formed onthe exposed surfaces of opposing pillars 106 and 108. The contaminantsmay be formed during a manufacturing process such as chemical mechanicalpolishing (CMP). CMP or other fabrication processes may leave a nativeoxide on top of the copper surface, and also may leave organiccontaminants on the surfaces of the pillars. The presence of suchcontaminants 120 may increase the temperature required for a subsequentsuccessful bond.

FIG. 3 shows the opposing substrates 102, 104 of FIG. 2 after opposingpillars 106, 108 have been bonded together. Contaminants 120 disposed onopposing bonding surfaces of the pillars may lead to disadvantageousbonds, 122. Contaminants 120 may prevent physical bonding, or may resultin a weakened physical bond 122. Moreover, the presence of an oxide filmon the bond surface of the pillar may also prevent grain growth acrossthe bonded interfaces, which could lead to a lower bond strength and/orvoid formation.

The bond 122 containing contaminants 120 may potentially result in orrepresent a total disruption in an electrical conduction path intendedalong a bonded pillar pair. For example, the oxide/contaminants may actas an interrupting or blocking electrical insulator barrier.Alternately, the bond may conduct electricity, but the resultingelectrical conduction path may be undesirable. The contaminants 120 mayincrease the total resistance of the electrical interconnections createdby bonding pillars due to the presence of a poor conductor, such as anoxide, at the bond interfaces 122.

An undesirable pillar bond may have devastating effects on themanufacturability and reliability of the 3D-IC. Proper formation andoperation of the bond/path of each pillar pair between opposing 3D-ICsubstrates may each be critical to an ultimate successful electricaloperation of the 3D-IC, and any failure of any bond/path at the time ofmanufacturing or at a subsequent time may render the 3D-ICunusable/inoperable. Accordingly, it is highly desirable that failuresbe avoided, so as to increase yield and reliability.

High temperature bonding offers one solution to the contaminant problemillustrated in FIGS. 2 and 3. A high temperature applied during abonding process tends to remove or de-oxidize the contaminants and/ormelt opposing pillar pair material (e.g., copper) together. However,high temperature bonding has itself been found to cause additionalproblems. For example, copper has very high diffusivity, even at roomtemperature. At elevated temperatures, the diffusivity of copper is evengreater. Thus, if high temperature bonding is performed, copper pillarmaterial may diffuse onto and/or into the substrate.

FIG. 4 illustrates the diffusion of copper pillar material 111 onto orinto the substrate 108. Diffusion may cause leaky conduction paths, mayeffectively decrease the electrical spacing between neighboring pillars,and may result in catastrophic short-circuiting and/or electricaldischarges, which may cause the IC to stop functioning. Furthermore,copper may diffuse into the dielectric portions of the substrate, whichmay increase leakage currents; or copper may diffuse into the active Sicomponents in the substrate, which could potentially render theminoperable. Because high temperatures typically exacerbate diffusion,high temperature bonding should be avoided as much as possible duringmanufacturing. Additionally, temperatures higher than 400-500° C. couldlead to the destruction of the circuit components formed within the ICsubstrate.

Thus, it is desirable to perform metal bonding of 3D-ICs at relativelylow temperatures in order to avoid reliability concerns. Clean coppersurfaces may enable low temperature bonding and result in lowerinterfacial resistances. One embodiment of the present invention detailspreparation of clean copper pillar surfaces to enable bonding at lowtemperatures. Low temperature bonding may be defined in a number ofways. For copper pillars, low temperature bonding may be defined asbonding effected at less than 250° C., or alternately, at less than 200°C., or still further, at less than 150° C. If different pillar materialother than copper is used, then a different low temperature may beapplicable. As an alternative definition, a low temperature may be anytemperature enabling less than or not more than a predetermined rate ofdiffusion of the pillar material during the bonding operation, forexample, enabling less than or not more than a predetermined rate of Xatoms/m²s, where X is a predetermined number, m is meters and s isseconds. Low temperature may also be defined in terms of ratio of bondtemperature to melting point. Using copper as an example, copper's bondtemperature to melting point is a ratio of approximately473K/1357K=0.34. Accordingly, pillar materials useable with embodimentsof the present invention may have a ratio of bond temperature to meltingpoint of <0.40, or more particularly <0.35. A lower ratio means that thematerial will bond at a low temperature in comparison to the meltingpoint; lower temperatures generally mean lower diffusion rates incomparison to a melting point diffusion rate where the materialtransforms from solid to liquid.

To prepare clean copper surfaces to enable bonding at low temperature,the copper surface may be cleaned by etching, chemical reaction and/orheating prior to bonding to obtain low interfacial resistance. Thefollowing examples detail processes used to prepare clean coppersurfaces to enable low temperature bonding.

Example Process Flow A (Chemical Cleaning):

Operation 1: The copper pillars 106, 108 of die or wafers to be bondedtogether as a 3D-IC may be exposed to a mixture of 1:1H₂O:HCl for about1 minute at room temperature. Practice of the present invention is notlimited thereto, and instead, other types of chemicals, mixtures and/ortimes may be used for cleaning, and especially if a pillar materialother than copper is used. Following this operation, the wafers arerinsed in distilled (DI) water and then dried. This operation may resultin clean copper pillars 106′, 108′ with pillar surfaces, includingbonding surface 109, having no native oxide or other contaminantsthereon, as illustrated in FIG. 5.

Operation 2: The cleaned die or wafers are loaded into an aligner tooland precisely aligned so as to align opposing pillars for bonding.

Operation 3: Immediately, or within a predetermined amount of time afterthe cleaning operation, the aligned die or wafers are then bonded usinga bonder tool at low temperatures (e.g., <200° C.) resulting in cleancopper-copper bonds or interfaces 110 illustrated in FIG. 6.Inter-substrate voids 170 are formed as framed by combinations of the ICsubstrates 102, 104 and neighboring interconnection pillar pairs 106′and 108′.

Example Process Flow B (Heat/Vapor Cleaning Prior to Bonding):

Operation 1: The copper pillars 106, 108 of die or wafers to be bondedtogether as a 3D-IC may be heated in a processing chamber to atemperature between 200-350° C. in an inert or reducing atmosphere or inhigh vacuum (<10⁻⁶ Torr).

Operation 2: The die or wafers may then be exposed to methanol vaporleaked in at low pressure of approximately 10⁻⁵ Torr for a short time ofapproximately 5-15 minutes. Methanol chemically reacts with Cu₂O to formgaseous products such as CO₂, CH₂O and CO. This treatment may remove anynative oxide present on the copper surface and other contaminants.Practice of the present invention is not limited to the temperatures,vapor, pressures and/or times given, and instead, other temperatures,vapor, pressures and/or times may be used for cleaning, and especiallyif a pillar material other than copper is used.

Operation 3: The die or wafers are then cleaned in acetone and ethanolto remove any organic contaminants, which results in a clean surfaceready to be bonded at a low temperature. Such operation results in cleancopper pillars 106′, 108′ with surfaces, including bonding surfaces 109containing no native oxide, as illustrated in FIG. 5.

Operation 4: The two die or wafers to be bonded are precisely alignedusing an aligner tool.

Operation 5: Immediately, or within a predetermined amount of time,after the cleaning operation, the aligned wafers are bonded using acommercial bonder tool at low temperatures (e.g., <200° C.) resulting inclean copper-copper bonds or interfaces 110, as illustrated in FIG. 6.Again, inter-substrate voids 170 are formed as framed by combinations ofthe IC substrates 102, 104 and neighboring interconnection pillar pairs106′, 108′. Voids 170 are advantageous because they are substantiallyfree of contaminants.

By providing a clean metal pillar surface, it may be possible to performthe bonding process at low temperatures (<250° C., <200° C., or <150°C.), which may reduce the manufacturing thermal budget significantly andwhich may also minimize undesirable copper diffusion during the bondingprocess. Advantages of embodiments of the present invention include: (1)copper-copper bonding at low temperatures, (2) lower interfacialresistance due to a clean metal-metal interface, (3) increased bondstrength due to a clean metal-metal interface, and (4) a lowermanufacturing thermal budget.

FIG. 7 illustrates a partial cut-away of substrates 102 and 104, andpillars 106′ and 108′. A thin pre-bonding layer 130 may be formed on allclean exposed surfaces of the pillars 106′, 108′. This thin layer mayprevent or minimize the diffusion of copper from the pillar during andafter bonding. Because copper has such a high diffusivity, copper pillarmaterial may diffuse onto and/or into the substrate even at roomtemperatures, if a diffusion barrier such as thin layer 130, is notused. The thin layer may also help to avoid or minimize electromigrationof pillar material. The thin layer also helps to prevent any corrosionof exposed pillar material. In one embodiment, the thin layer 130 may bea metal film having a thickness of less than 10 μm or less than 10 Å.More particularly, the passivation material may be formed at a thicknesswithin a range of 0.01-0.03 μm.

The thin layer may be selectively deposited on the surfaces of copperpillars 106′ and 108′ to serve as a diffusion barrier for the copper.Self-assembly of a conductive coating on the copper surface is oneoption that may be used to form the thin layer, e.g., using a materialwhich selectively deposits only on copper. Upon bonding, the coatingspreads on the copper sidewall and protects it from any corrosion orelectromigration. Potential metals that may be used to form the thinlayer include, Ta, Ti, Mg, Al, but practice of the present invention isnot limited to such example metals. In another embodiment, a noblemetal, such as silver or gold, may be used to form the thin layer. Thechoice of an appropriate thin layer material for any givenimplementation may depend upon the choice of pillar material.

The thin pre-bonding layer 130 may alternately be formed by thedeposition of a few monolayers of a metal thin film by atomic layerdeposition (ALD) selectively on the copper. Any known ALD process may beused. Atomic layer deposition has excellent step coverage and can filltrenches effectively since the growth mechanism is a layer-by-layermode.

FIG. 8 illustrates the substrates 102, 104 and pillars 106′, 108′ afterhaving been subjected to a bonding operation. In one embodiment,portions of the thin layers 130 may remain sandwiched between eachpillar pair 106′,108′, and may participate in the bond 132. In suchcase, care should be taken to ensure that a material of the thin layers130 will help provide a sufficient bond responsive to the subjectbonding operation of record (BOOR). That is, a sufficient bond 132should be established not only between the opposing thin layers 130, buta sufficient bond should be established or maintained between each thinlayer 130 and the pillar material (e.g., Cu). Bonding with the thinlayers 130 should also accommodate pillar deformation and/or creep. Thethin layer material should be selected to provide stable, long-termprotection throughout the anticipated life of the 3D IC.

In another embodiment, the methods and materials described above may beused to enable low temperature bonding between a single die or 3D stackof die having copper C4 bumps and a package having copper solder bumps.Although the terms “C4 bump” and “solder bump” are typically used todescribe structures comprised of an alloy of metals such as lead andtin, these terms are being used herein to describe structures having thesame function as a typical C4 bump or solder bump, but comprised of asingle homogenous metal, such as copper, or alloys of other metals.

FIG. 9 illustrates an example three-dimensional cross-sectional view 200of a small portion of a die 204 bonded to a package substrate 202according to an embodiment of the present invention. The packagesubstrate 202 may be a printed circuit board (PCB). The packagesubstrate 202 has a plurality of solder bumps 206, which may becomprised of copper or another conductive material, such as aluminum,gold, silver, or alloys of two or more elements. The die 204 has aplurality of C4 bumps 208, which may be comprised of copper or anotherconductive material, such as aluminum, gold, silver, or alloys of two ormore elements. The solder bumps 206 and C4 bumps 208 are shown assquares for the purposes of illustration only, and may be spherical inshape. The solder bumps and C4 bumps are typically much wider than thepillars described above, and may be as large as 70-100 microns wide, orsmaller.

The solder bumps 206 on the package are bonded to the opposing C4 bumps208 on the die to form electrical interconnections between the die andthe package. While embodiments describe the C4 bumps and the solderbumps as being made of a mutually common material such as copper,embodiments of the invention is not limited thereto. The C4 bumps andsolder bumps may be made of mutually differing materials, so long as thetwo materials may physically bond together to form an electricalconduction path.

As described above with respect to copper pillars, the copper surfacesof the C4 bumps and the solder bumps may be cleaned prior to bonding toenable bonding to occur at low temperatures. The copper C4 bumps and thecopper solder bumps may be cleaned using an acid etch or chemicalcleaning, as describe in example process flow A, above. Alternately, thecopper C4 bumps and copper solder bumps may be cleaned using heat/vaporcleaning, as described in example process flow B, above. The copper C4bumps and copper solder bumps may also be cleaned by performing a gasanneal to remove any native oxide.

FIG. 10 illustrates a cross-section of package substrate 202 and die 204after the copper solder bumps 206′ and copper C4 bumps 208′ have beencleaned to remove any contaminants that may have been present on thecopper surfaces. The cleaning operation results in copper solder bumps206′ and copper C4 bumps 208′ having clean surfaces, including cleanbonding surfaces 209.

Next, as illustrated in FIG. 11, a thin layer of metal 230 may be formedselectively on the clean copper solder bumps 206′ and the clean copperC4 bumps 208′. This thin layer may prevent or minimize diffusion ofcopper from the solder bumps and C4 bumps during and after bonding. Thethin layer may also help to avoid or minimize electromigration of coppersolder bump and copper C4 bump material, as described above. In oneembodiment, the thin layer is comprised of a noble metal, such assilver. Other noble metals, including gold, platinum, palladium, osmium,iridium, ruthenium, or rhodium, may potentially be used to form the thinlayer as well.

The use of a thin layer material which has a low solubility in the bumpmaterial is desirable to enhance resistance to electromigration and toprevent voiding in the solder bumps and C4 bumps. A low solubility isdefined as less than 1% solubility at 400° C. Silver, a noble metal, haslow solubility in copper (less than 0.5% at 400° C.), and thus the thinlayer of silver used to coat the copper surfaces may enhance resistanceto electromigration and may prevent voiding in the copper solder bumpsand the copper C4 bumps. The thin layer may also reduce or preventcorrosion of the copper solder bumps and copper C4 bumps.

The thin layer 230 of silver may be deposited selectively on the cleancopper solder bumps 206′ and on the copper C4 bumps 208′ usingdisplacement deposition. By depositing the thin layer in this manner,the silver may be deposited only on the copper surfaces and not on thesurface of the substrate. Alternately, the thin layer may be depositedover both the copper surfaces and the exposed surfaces of the die orpackage substrate by sputtering, electro-beam evaporation from a silvertarget, chemical vapor deposition, or atomic layer deposition (ALD). Ifthe thin layer is deposited over the entire surface using one of thesedeposition techniques, the process may be followed by a maskingoperation to mask the coated copper bumps, and an etch to remove thesilver from the substrate surface, leaving the silver film only on thesurfaces of the copper bumps.

The thin layer 230 formed on the copper bumps may range in thicknessfrom approximately 40 to 100 nm. More particularly, the thin layer maybe approximately 50 nm thick.

After forming the thin layer of noble metal on both the copper solderbumps on the package substrate and on the copper C4 bumps on the diesubstrate, the die and package to be bonded may be precisely alignedusing an aligner tool. The die and package may then be bonded togetherat low temperatures (e.g., <300° C.).

FIG. 12 illustrates the die 204 and package 202 substrates after thecopper C4 bumps 208′ have been bonded to opposing copper solder bumps206′. In one embodiment, portions of the thin layers may remainsandwiched between each copper bump pair 206′, 208′, and may participatein the bond 232. The thin layer of noble metal 230 which coats thecopper bumps 206′ and 208′ may decrease the diffusion of copper into theother substrate materials. The use of silver as the thin layer metal mayalso prevent out-diffusion and voiding of the copper, because silver hasa very low solubility at room temperature and thus it is unlikely thatthe silver would diffuse into the copper to form a solid solution.

FIG. 13 illustrates an example electronic system arrangement that mayincorporate implementations of the present invention. More particularly,at a low level, shown is a 3D-IC that may incorporate one or moreimplementations of the present invention as a 3D-IC system. The 3D-ICmay be further mounted as part of an electronic package PAK systemincorporating the 3D-IC together with supporting components (e.g., avoltage regulator, decoupling capacitors, etc.) onto a substrate (suchas a printed circuit board (PCB)). The PAK system may also incorporateone or more embodiments of the present invention in the die or 3D-IC topackage bonds. The PAK system may be further mounted, for example, via asocket SOK onto a system printed circuit board PCB (e.g., a motherboardsystem). The system board may be part of an overall electronic device(e.g., computer, electronic consumer device, server, communicationequipment) system 100 that may also include one or more of the followingitems: input (e.g., user) ports B, output ports (e.g., display DIS,audio system), other peripheral ports (e.g. printer, internetconnections, etc.), a bus or bus portion BUS, a power supply arrangementPS, other integrated circuits and chipsets, and a case CAS (e.g.,plastic or metal chassis).

Although example embodiments of the present invention have beendescribed using example 3D-ICs and/or 3D WSs having two layers and usingcopper (Cu) pillar interconnections there-between, practice of theinvention is not limited thereto. For example, the invention may be ableto be practiced with more than two layers, with other types ofsubstrates, with other (non-pillar) types of interconnections, and withother types of materials besides copper (e.g., aluminum (Al), gold (Au),silver (Ag)).

1. A method comprising: coating a conductive bump on a first substratewith a conductive material to form a coated conductive bump; coating aconductive bump on a second substrate with a conductive material to forma coated conductive bump; and bonding the coated conductive bump on thefirst substrate to the coated conductive bump on the second substrate toelectrically connect the first substrate to the second substrate.
 2. Themethod of claim 1, wherein the conductive bumps are comprised of copper.3. The method of claim 1, wherein the conductive material comprises anoble metal.
 4. The method of claim 3, wherein the noble metal comprisessilver.
 5. The method of claim 3, wherein bonding occurs at atemperature lower than 300° C.
 6. The method of claim 5, wherein thefirst substrate is a semiconductor die substrate and the secondsubstrate is a package substrate.
 7. The method of claim 5, wherein thefirst substrate and the second substrate are semiconductor substrates.8. A method comprising: forming a layer of a conductive material on afirst set of copper bumps provided on a first substrate to form a firstset of coated copper bumps; forming a layer of a conductive material ona second set of copper bumps provided on a second substrate to form asecond set of coated copper bumps; and bonding the first set of coatedcopper bumps to the second set of coated copper bumps.
 9. The method ofclaim 8, wherein the first substrate is a semiconductor die substrateand the second substrate is a package substrate.
 10. The method of claim8, wherein the first and second substrates are semiconductor substrates.11. The method of claim 8, wherein the conductive material comprises anoble metal.
 12. The method of claim 8, wherein the noble metalcomprises silver.
 13. The method of claim 12, wherein the layer ofsilver is formed by displacement deposition.
 14. The method of claim 12,wherein the layer of silver is formed by one of: sputtering,electro-beam evaporation from a silver target, chemical vapordeposition, atomic layer deposition followed by an etch-back.
 15. Themethod of claim 8, wherein bonding occurs at a temperature lower than300° C.
 16. The method of claim 8, further comprising cleaning thesurface of the copper bumps before forming a layer of a noble metal onthe copper bumps.
 17. The method of claim 16, further comprisingaligning the first set of copper bumps on the first substrate with thesecond set of copper bumps on the second substrate before bonding. 18.The method of claim 16, wherein the surface of the copper bumps iscleaned using one of an acid etch, exposure to methanol vapor, or a gasanneal to remove any native oxide.
 19. A method comprising: cleaning afirst set of copper bumps provided on a first substrate; cleaning asecond set of copper bumps provided on a second substrate; forming alayer of silver on a first set of copper bumps provided on a firstsubstrate to form a first set of coated copper bumps; forming a layer ofsilver on a second set of copper bumps provided on a second substrate toform a second set of coated copper bumps; aligning the first set ofcoated copper bumps on the first substrate with the second set of coatedcopper bumps on the second substrate; and bonding the first set ofcoated copper bumps to the second set of coated copper bumps at atemperature of less than 300° C.
 20. The method of claim 19, wherein thesurface of the copper bumps is cleaned using one of an acid etch,exposure to methanol vapor, or a gas anneal to remove any native oxide.21. The method of claim 19, wherein the layer of silver is formed bydisplacement deposition.
 22. The method of claim 19, wherein the layerof silver is formed by one of: sputtering, electro-beam evaporation froma silver target, chemical vapor deposition, atomic layer depositionfollowed by an etch-back.
 23. The method of claim 19, wherein the firstsubstrate is a semiconductor die substrate and the second substrate is apackage substrate.
 24. The method of claim 19, wherein the first andsecond substrates are semiconductor substrates.
 25. A device comprising:two stacked substrates; and a plurality of conductive bumps provided oneach substrate, wherein each of the plurality of conductive bumps iscoated with a conductive material and opposing coated conductive bumpsare bonded to one another to electrically connect the two stackedsubstrates.
 26. The device of claim 25, wherein each of the plurality ofconductive bumps is comprised of copper.
 27. The device of claim 25,wherein the conductive material comprises a noble metal.
 28. The deviceof claim 27, wherein the noble metal comprises silver.
 29. The device ofclaim 28, wherein the two stacked substrates comprise a semiconductordie substrate and a package substrate.
 30. The device of claim 28,wherein the two stacked substrates comprise semiconductor substrates.